Integrated circuits (ICs) are manufactured and tested in wafer form before being diced from the wafer and mounted in packages, modules, or directly on a printed circuit board. Wafer level IC testing is a critical part of the IC manufacturing process that identifies ICs that do not function properly and provides feedback for repair through programming of redundant logic as well as improving product design and reducing manufacturing cost. Wafer level IC testing also prevents non-functioning ICs from going through the cost of packaging and in some cases can be used for stress testing or burn-in testing at high temperature to screen ICs to improve long term reliability.
Conventional wafer IC testing uses probecards to provide an electrical path between a test system and the pads on integrated circuits while in wafer form. Probecards generally have electrical contact points that match the size and density of the electrical pads on an integrated circuit and conductive patterns that provide the fan-out of electrical signals from these pads to the much larger printed circuit boards and connectors that interface to the test system. The probecard is typically held in place on a wafer prober which moves the IC wafer pads into position to make an electrical connection with the contact points on the probecard. After an integrated circuit or an array of integrated circuits has been aligned, contacted by the prober, and electrically tested, the prober moves the IC wafer to the next integrated circuit or array of integrated circuits so the next set of tests can be performed. The prober generally uses automatic pattern recognition optics to align the contact pads on the wafer and the tips of the probes. After the wafer is in alignment for a test, the prober very precisely raises the wafer to push the probe contact points against aluminum, solder, or other metal pad materials on the integrated circuits. The prober must raise the wafer high enough to create sufficient force to break through any oxides on the integrated circuit's metal pads and make a reliable electrical contact but not so high that probe tips slide off the pad or that the probe tip force causes damage to the circuits under or near the IC pads. This mechanically breaking through the oxide to make an electrical contact is commonly referred to as scrub and the mark left on an IC pad is called a scrub mark. The probecard must compensate for mechanical tolerances in the manufacturing of: 1) the IC wafer, 2) the probe contact points, 3) the probecard electrical interconnect (printed circuit boards, ceramic substrates, flex circuits) and 4) the prober. The probecard must also be designed to compensate for any mechanical movement due to heating of the wafer from the power generated by integrated circuits or by the prober performing high temperature testing as a reliability screen. The probecard must maintain low contact resistance, consistent probe force and alignment during its operating life. Some probecards applications can require a contact life of over a million test cycles.
The semiconductor industry's growth has been driven by delivering faster, smaller, more complex ICs at lower cost. Typically the number of transistors on an IC doubles every 18 to 24 months. This trend requires the test time to increase and the number of interconnect pads on the IC to increase while the pad pitch and size shrink and the frequency at which the IC operates goes up. High frequency operation with a large number of pads significantly increases the bandwidth of an integrated circuit. For high bandwidth applications, the probecard must also supply large amounts of DC and AC current to power and ground pads and supply signals to input/output pads while not generating noise that affects testing results. Due to electrical limitations, most probecard technologies cannot replicate the high frequency environment that high bandwidth ICs require. These limitations become even more severe as the frequency and number of signals on an IC increase. As a result, traditional techniques for building probecards cannot meet these performance demands. The result of testing with traditional techniques can be the rejection of some good ICs that testing falsely classifies as bad units.
Also, the cost of testing ICs has been rapidly growing as a percentage of the total costs to manufacture ICs. The increasing number of transistors, number of pads and higher frequency operation increases the tester costs and time needed to test ICs. One way to reduce the cost of testing is to test a larger number of ICs at the same time. This higher parallelism improves the test system utilization and reduces the total wafer test time and thus reduces the overall cost of testing. The ultimate level of parallel testing is to test all of the ICs on a wafer at one time.
Most conventional probecards use electrical springs that are designed to be long enough to compensate for the mechanical tolerances and thermal movement encountered while testing in a wafer prober. These springs (or probes) are relatively long (4-8 mm), run parallel to each other and therefore cannot run at high frequency (>1 GHz) due to high mutual and self-inductance. Even at lower frequencies (<100 MHz), high inductance probes have more electrical noise which results in lower test yield (i.e., good ICs are categorized as bad devices).
FIG. 1 is a drawing of a conventional cantilever probe. Each cantilever probe traditionally is manufactured using a tungsten wire 2 with a small tip that is used to contact the aluminum pads of an IC. The probe 2 is generally mounted on a PCB 1. During testing, sufficient force must be applied to the tip of probe 2 as an IC wafer is raised to make a reliable electrical connection by breaking through the oxide (e.g., aluminum oxide) on an IC pad. To keep tungsten probes 2 from deforming or cracking, probes 2 need to be long enough to distribute the stress along the beam. This means a typical probe 2 is more than 5 mm long. The manufacturing process needed to align these probes to the pads on an IC is a manual mechanical placement technique which becomes increasingly difficult to perform as the spacing of the electrical pads become closer together. In most applications, these probes are too long to escape all the signals on a single IC in the space of the IC. This means for full wafer testing their use is restricted to very low pin density applications such as NAND Flash ICs that have relatively large die size with low pin counts or BIST (Built in Self Test) circuits that have fewer than 12 pins per IC. If the cantilever spring is damaged during probing, the repair process generally produces a less reliable probe. The positioning of the repaired probes tends to drift off of the IC pad with increased use. Cantilever probes cannot scale to meet the needs of testing at higher frequencies when migrating to a finer pad pitch. Tighter spacing significantly increases the inductance of the probes. This means that cantilever probes have limited applications for simultaneously contacting all of the pads on a single wafer.
Another conventional approach that has been applied to full wafer testing and burn-in is the use of vertical wires that can flex as an IC wafer is being raised to make an electrical connection. This flexing compensates for the planarity difference between the IC wafer being tested and the probecard PCB (printed circuit board). One approach, as shown in FIG. 2, for manufacturing this type of probecard is to align vertical wires 11 between two plates 10 and 12 with through holes having a slight off-set 13 from each other. The offset 13 provides a predefined bias to the direction the probe wires 11 will bend. The predefined bias keeps probe wires 11 in an array from randomly buckling which could result in adjacent probes shorting together. These vertical wires 11 can buckle enough to compensate for the planarity difference are commonly called buckling beam probes or cobra probes.
One end of a buckling beam probe typically makes electrical contact to a pad on a space transformer that fans out to the electrical connection in the PCB portion of the probecard. The other end of the probe makes electrical contact to the pad on the IC being tested. The space transformer and buckling probes are generally attached to the probecard using a mechanical fixture. This fixture uses adjustment screws to change the tilt of the space transformer so that the probe tips can be made to be parallel to the probecard and/or wafer to be tested.
Another traditional prober system uses a pogo pin which is held in a block that aligns to the IC pads. A pogo pin 20, as shown in FIG. 3, includes a narrow cylinder or barrel that has two spring loaded pins inserted into each end of the cylinder. The pins compress inside of the barrel to compensate for planarity differences as the wafer is pushed into contact with the pogo pins. An example of a pogo pin is shown in FIG. 3.
Both the buckling beam and pogo pin probes need to have long lengths (4-8 mm) to compensate for the planarity mismatch between the printed circuit board that interfaces to the tester and the IC wafer being tested. Also, as IC pad pitch shrinks, the frequency performance of these approaches is reduced. The result can be that good ICs are rejected as bad units. Smaller springs needed for tighter pad pitches are usually more expensive. The above mentioned vertical spring approaches cannot meet the performance or cost needs of IC testing as ICs continue to scale to tighter pitches, higher pin counts and larger probing areas. However, these springs have an advantage in that they are relatively easy to repair when damaged. A damaged spring can be manually removed and replaced with a new spring.
A membrane probe is a prior art approach that typically uses a polyimide film with contact tips. FIG. 4A is a drawing of a membrane probe 80a. The compliance of the membrane probe comes from using a flexible film and the force is generated using an elastomer material 68 under the film as shown in FIG. 4B. This elastomer provides a vertical force but it is distributed over the membrane and not focused just on the contact tips 92. Since there is not enough focused force to make a reliable electrical contact to aluminum pads 93 with the elastomer, the tips have been designed to instill a rocking motion to break through oxides on the surface of the aluminum pads and create a small scrub. An example of this tip is shown in FIG. 4B. The tip of the membrane probe must also be raised above the surface of the polyimide film high enough that the film does not touch other parts of the wafer during test. Membrane probes are capable of high performance testing because they can maintain controlled impedance while routing signals to the pins under test. Membrane probes fan out the signals from an IC pitch to a larger PCB pitch. As the number of signals increases, this routing can either be accomplished by using longer and narrower traces or by using a thicker membrane with more layers. The resistance of long narrow traces will not meet the requirements for testing a full wafer of memory ICs. Using more routing layers makes the membrane rigid and it is no longer flexible enough to provide enough compliance to accommodate the planarity differences between the IC wafer and the probecard PCB. Membrane probes are currently fabricated in a 100 mm format. As the size of the manufacturing format grows, the dimensional stability of the membrane is not adequate to stay aligned to the IC pads needed for testing 200 mm or 300 mm wafers. Larger formats also become prohibitively expensive. Even in single IC testing applications, if a membrane is damaged, the entire membrane must be replaced which is a large expense.
Flexible wires have been created as shown in FIG. 6. Such wires can be bonded to a substrate and bent to a shape that that allows the wires to flex. The wire can be plated with nickel to give the wire the required fracture strength and to provide sufficient force to break through the oxide on an IC pad. A custom tip shape is bonded to the top of the wire spring to enable a reliable electrical contact during testing. These wire springs generally need to be between 3-5 mm long to provide enough compliance and force to make electrical connections during probing. These springs can be bonded to a HDI (High Density Interconnect) substrate surface. They are difficult to replace, and repair is limited to springs that are easily accessible near the perimeter of the array of springs.
The traditional probes were designed to test a single IC or a few ICs in parallel. These probes typically needed to test an area less than 15 mm×15 mm. This small testing area allows springs to be fanned out directly to the tester printed circuit board beyond the probe contacting area. Recently, probecards capable of probing a memory wafer with as few as four touchdowns (a quarter of a 300 mm at one time) have been introduced. These probecards need to probe a much larger area and have a probe area size that is at least 160 mm×160 mm. These probecards can simultaneously test as many as 256 DRAMs in parallel. This means that all of the probe contact points for a single IC must escape within the space dictated by the size of the IC. The traditional cantilever probes are too large to escape in the area of a typical memory IC. Although traditional vertical or buckling beam probes can escape within a DRAM die array, they became prohibitively expensive as these probes need to shrink in size when over 10,000 vertical probes are needed to make contact to fine pad pitches of DRAM devices.
MEMS (Micro-Electro-Mechanical Systems) spring based probecards were introduced for the large area and higher pad densities required for parallel memory testing (32 to 256 RAMs tested at one time). These probes are shorter than traditional probes and are capable of fitting within a memory die size. To be able to escape all of the probes within a die site, these probes are mounted on a HDI which serves four purposes: 1) fan out the IC pad density to a pad density that can be routed on a printed circuit board, 2) provide a rigid structure that minimize flexing due to force generated during testing with the very large number of springs, 3) provide a vertical translation (probe depth) to fit in older probers and 4) be able to be become planar to the wafer under test.
An example of the most common MEMS probecard architecture is shown in FIG. 7. The HDI 190 is a multi-layer co-fired ceramic held in place on the top of the HDI with brackets 195. The ceramic thickness is typically 5 to 11 mm. An interposer 191 is placed between the ceramic and the tester PCB to compensate for the planarity between the ceramic and the PCB. The interposer allows the test head (HDI with mounted MEMS springs 194) to be removed for repair and to be mechanically adjusted using screws 193 to align the MEMS spring 194 tips so that they are parallel to the IC wafer being tested.
FIG. 8 is an example of a MEMS spring suitable to be used with the co-fired ceramic space transformer. Each spring 30 is a nickel based spring that is typically 1.5 to 2.0 mm long and 300 microns tall. The spring length is needed to create sufficient force (1.5-3 grams per mil of over drive) to achieve low electrical contact resistance when probing aluminum pads. If the length of the beam 31 is reduced, the nickel beam will fracture during its required lifetime (100,000 to 1,000,000 contacts). This type of MEMS spring has individual springs soldered to the HDI. Repair is very difficult at the customer's manufacturing line and repair is typically limited to springs near the perimeter of an array.
Another MEMS based architecture is shown in FIG. 9. The architecture consists of a probecard PCB 211, a z-block for probe depth adjustment 408, two interposers 406 and 409 with one on either side of the z-block, and an HDI 502 with springs 72 such as shown in FIG. 11 attached. These MEMS based springs use a batch process to fabricate them on a relatively thin ceramic based HDI. The HDI is attached to a “compliant membrane or mesh 552 that keeps the bottom interposer fully compressed at all times by controlling the flex in the decal. The two interposers compensate for planarity differences between the two sides of the z-block, the HDI and the tester PCB. A disadvantage of this approach is that the interposer that makes electrical contact between the z-block and the thin HDI has vertical springs near the active area of the probe and not along the edges of the HDI where it is supported by the compliant membrane or mesh. This force differential can cause the HDI to bow or tent and causes a planarity error at the tips of the probes. This is the same effect as reported in U.S. Pat. Pub. number US2007/0057685, entitled “Lateral Interposer Contact Design and Probecard Assembly” and results in a convex bow 503 as shown in FIG. 10. This convex bow reverses and becomes a concave bow as the wafer under test pushes against the probes. These swings in planarity affect the alignment of the probe tips to the pads being tested. As the pad sizes on the ICs shrink and the number of probes increases, these types of probecard architectures cannot stay aligned to the pads and have a different amount of mechanical scrub depending on the probes location on the HDI. Poor alignment can damage the insulating layer around the IC pads and insufficient mechanical scrub can affect the electrical reliability of the pad to probe contact.
The MEMS spring 72 used in the architecture of FIG. 9 is shown in FIG. 11. The length of this probe is shorter than the MEMS spring 30 shown in FIG. 8. Being a shorter spring, the electrical parameters are better but this type of spring makes contact to the IC pads with a shallow angle which results in a longer scrub mark. As IC pads shrink to smaller sizes it is difficult for probes/springs 72 to scale to the smaller pad areas. These probes need a height of approximately 200 microns to compensate for the planarity difference in the architecture. As the area expands to full wafer memory testing, this architecture will result in a stack up of tolerances that cannot be managed without increasing the spring height. Further, these springs 72 are a batch fabrication on the HDI and cannot be repaired if damaged. The entire probe head must be replaced.
An example of an interposer that limits the vertical force of an interposer on a HDI is shown in system 505 of FIG. 12. A lateral force is applied to the interposer springs for electrical contact. This reduces the vertical force which contributes to the initial bowing of the HDI.
In all of these interposer and HDI based architectures, the probecard is assembled and the frame holding the HDI/probes is adjusted using screws to minimize tilt or bow that affects the x-y-z alignment of the probes to the IC pads. However, this alignment cannot be maintained while the frame is being distorted by the mechanical and thermal forces experienced during the wafer testing process. As the number of IC pads and temperature testing extremes increases, these architectures have difficulty scaling to match the needs.
Another problem encountered when attempting to test a full wafer at one time is that it is difficult to successfully build (yield) a large number of probes (up to 50,000) on the HDI over the area of a 300-mm wafer. One approach to improve the yield is to build smaller HDI substrates with probes in place that are known to be good and then electrically solder or adhesively assemble these “tiles” in place on a larger (>300 mm) substrate. This assembly process must closely control the solder volume or the adhesive thicknesses and the thickness of the individual tiles in order to keep the height of the probes planar over the 300 mm area.
The approaches listed above are attempts to scale probecards to meet the needs of contacting smaller pads, at higher densities and higher frequencies while meeting the mechanical demands of maintaining an excellent electrical contact over larger probing areas and at high temperatures. The approaches attempt to balance the conflicting demands of needing shorter, controlled impedance electrical paths to meet the electrical and density needs against the requirements for longer electrical springs to provide greater mechanical compliance. Many of the traditional approaches cannot probe larger areas because they need to fan out laterally to route out to the tester connectors. Traditional approaches cannot scale to performing high performance testing while simultaneously providing electrical connections to all of the ICs on a full wafer. Scaling of the HDI to match 300 mm and larger wafers is prohibitively expensive.